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NAIST Application NoP10-04



TitleASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD
INVENTOROHTAKE, Satoshi;IWATA, Hiroshi; INOUE, Michiko.
Pub.NoWO/2011/158500Pub Date2011/12/22
International Application NoPCT/JP2011/003405International Application Date 2011/06/15

abstractThe disclosed asynchronous memory element for scanning is provided with an n-input asynchronous memory element (12), and a scan control logic circuit (14) that generates the n-input for the asynchronous memory element (12) from an n-bit signal input and scan input. The scan control logic circuit (14) outputs, as the n-input for each asynchronous memory element (12), a signal input when the control signal applied is a first bit pattern, a scan input when the signal is a second bit pattern, and a bit pattern where the asynchronous memory element (12) retains a previous value at all other times.
National Phase